Friday, October 20, 2017
   
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faq-icon.png ABTR-CPU Specific - ARM
Knowledgebase Articles
  • KB00048 - Catch all exception vectors on an ARM 964E CPU

    Question: How do I configure the BDI probe to catch all exception vectors on my ARM946E CPU?

    Answer:
    When using the bdiGDB firmware, add/modify the lines in the config file

    [TARGET]
    .
    .
    STARTUP..... RESET
    VECTOR .......CATCH..... 0xff

    The problem is that with STARTUP RUN, the ARM964E vector catch register is not set via the BDI. Use STARTUP RESET then enter "go" at the telnet prompt.
    Hits : 116
  • KB00049 - ICEBreaker access check failing from the RESET command?

    Why is the ICEBreaker access check failing from the reset command?

    Answer:

    1.) Please Check the JTAGSEL line on the ARM chip and make sure that it is pulled high rather than low.

    2.) The default JTAGCLOCK speed has been changed with newer firmware to 16Mhz. If this is too high for your ARM chip then try to change the JTAGCLOCK back to 8Mhz.

    Hits : 136
  • KB00050 - ARM Semi-hosting support

    Question:
    Is ARM Semi-Hosting supported by the BDI probe?

    Answer:
    bdiGDB uses the standard GDB remote protocol. There is no semi-hosting possible with it.

    If you're using an RDI compliant debugger rather than GDB, Abatron's bdiRDI-ARM7/9 firmware supports semi-hosting.

    Hits : 144
  • KB00124 - Where can I find BDI config files for TI boards

    Question: 

    Where can I BDI configuration files for my TI hardware?

    Answer:

    Matt Porter from TI published some useful files at:
    https://github.com/ohporter/bdi_configs

    You can also find additional .cfg and RegDef files at Abatron's FTP site:

    ftp://94.230.212.16/bdigdb/

    Hits : 142
  • KB00127 - Does the BDI probe work with the Xilinx Zynq 7000 Series of FPGA's

    Question:
    Does the BDI probe work with the Xilinx Zynq 7000 Series of FPGA's

    Answer:
    The Zynq-7000 EPP family of FPGAs embed the Dual Core Cortex-A9 and they all leverage the 28nm scalable optimized programmable logic used in Xilinx’s 7 series FPGAs. Each device is designed to meet unique requirements across many use cases and applications. Z-7010 and Z-7020 are leveraging the Artix™-7 FPGA programmable logic offering lower power and lower cost targeting high-volume applications, and Z-7030 and Z-7045 are based on the Kintex™-7 FPGA programmable logic for higher-end applications that require higher performance and high I/O throughput.

    We recommend you use the .cfg file named "Zynq_Tested" which can be downloaded from Abatron's FTP site at:

    ftp://94.230.212.16/bdigdb/config/arm/cortex-a/
    Hits : 227
  • KB00128 - Trouble Connecting My BDI2000/3000 to a Freescale i.MX6 CPU board

    Question:
    I am having trouble connecting my BDI2000/3000 to my board that has an iMX6 CPU from Freescale.  Any idea what could be my problem?

    Answer:
    Be sure you are using version 1.16 of the firmware, bdiGDB-ARM11-Cortex.  This version of the firmware provides an option for "IDLE" startup mode which is necessary for iMX6 and Tegra2 processors if you plan to connect to more than only the the active core #0.  Look at the release note as well as the i.MX6 configuration example distributed with version 1.16 of the firmware.

    You can also download this config files from the FTP site below.

    ftp://94.230.212.16/bdigdb/config/arm/cortex-a/

    Hits : 400
  • KB00129 - Trouble Connecting my BDI2000/3000 to nVidia's Tegra2 hardware

    Question:
    I am having trouble connecting my BDI2000/3000 to my board that has an nVida Tegra 2 (Cortex-A9) CPU on board.  Any idea what could be my problem?

    Answer:
    Be sure you are using version 1.16 of the firmware, bdiGDB-ARM11-Cortex.  This version of the firmware provides an option for "IDLE" startup mode which is necessary for the Tegra2 processors especially if you plan to connect to more than only the the active core #0.  Look at the release note and review the Tegra 2 configuration example distributed with version 1.16 of the firmware.

    You can also download this config files from the FTP site below.

    ftp://94.230.212.16/bdigdb/config/arm/cortex-a/

    Hits : 116
  • KB00136 - Does the BDI2000/3000 require TRST for ARM/Cortex CPUs?

    Question:
    Do I need to have TRST brought out on my JTAG debug port to use the BDI probe?

    Answer:
    The BDI3000 will work with targets which have no dedicated TRST pin. For this kind of target, the BDI cannot force the target to debug mode immediately after reset. The target always begins execution of the application code until the BDI has finished programming the Debug Control Register.

    Note that Abatron provides a version of firmware (bdiGDB-ARM11-SWD) that supports ARM's low pin count interface known as SW-DP or Serial Wire Debug Port.  For more details, refer to USI's KB article # KB00137.

    Hits : 205
  • KB00137 - BDI2000/3000 SWD Support for Cortex CPUs

    Question:
    What is Single Wire Debug and why would I use it?

    Answer:
    For Cortex-M3/M4 & Cortex-A8/A9 the BDI3000 supports the "Serial Wire Debug" Port (SWD or SW-DP). In orderto use SWD feature, users must load different firmware into the BDI3000 (included on the CD). Also a special target cable is available on request (P/N USI07-90054).  Refer to page 10 & 11 of the User's Manual for more details about this low pin count debug port.

    The SW-DP provides a low pin count bi-directional serial connection to the DAP with a reference clock signal for synchronous operation.  Communications with the SW-DP use a three-phase protocol:

    • A host-to-target packet request.
    • A target-to-host acknowledge response.
    • A data transfer phase, if required. This can be target-to-host or host-to-target, depending on the request made in the first phase.

    Hits : 197
  • KB00143 - Can't connect my BDI2000/3000 to Broadcom's BCM5301x (Cortex-A9) Target

    Question: 
    I can't seem to get my BDI to connect to my Broadcom BCM5301x (Cortex-A9) SoC.  Do you have any suggestions as to what my problem may be?

    Answer: 
    Broadcom's BCM5301x (StratGX) line of Communication Processors with Network Accelertion.  We learned that this SoC isn't 100% compliant with ARM's CoreSight Specs.

    The BCM5301x SoC does not behave as expected as it relates to bit-31 of the APB address. Normally bit-31 is not actual an address bit but qualifies the access if it comes from external or internal source.

    Abatron had to modify the bdiGDB-ARM11/Cortex firmware in order to support this chip.  In our opinion this chip is not 100% compliant with ARM's CoreSight debug architecture or Abatron has misinterpreted the spec.  The reason we've come to this conclusion is that all other Cortex-A8/9 chips Abatron has worked with behave as expected.

    USI has a working config file is named "BCM5310x_northstar_Cortex-A9.cfg"

    There were a couple of things that needed to be addressed.  Ruedi & Steve Goodell @ Broadcom can probably provide more details:

    1.  Force debug address of the CPU's  in the config file.  Not sure why BDI couldn't detect the addresses?  This problem has been fixed now in v1.17 of bdiGDB-ARM11/Cortex.
    2.  Clear bit 31 on debug accesses.  The BCM53012 chip wasn't responding to debug access with bit 31 set.  This required a firmware update that Ruedi provided.  Steve has brought this to the attention of his chip designers.

    -Steve Goodell is the technical contact at Broadcom who has expericence using the BDI3000 with these SoC's

    The latest test firmware (B30a11gd_beta117) accepts an APB debug address below 0x80000000. This firmware responses with V0.99.  Ruedi modified the firmware a bit more so it should now be able detect the debug base addresses automatically.

    Please load the beta firmware and try the following congiuration.  There in no longer a need to force the APB debug addresses.  Note that version 1.17 of bdiGDB-ARM11/Cortex will have this fix applied so the beta firmware won't be needed.  Your configuration should now read:

    #0 CPUTYPE  CORTEX-A9  0 ;use first detected core

    #1 CPUTYPE  CORTEX-A9  1 ;use second detected core

    Hits : 199
  • KB00152 - Can the BDI support CSAT(Core-Side Access Tool) for ARM?

    Question:

    Can the BDI support CSAT(Core-Side Access Tool) for ARM?

    Answer:

    Core Sight Access Tool is the front end for ARM's own JTAG probe RealView-ICE hardware and it is specific for that hardware.  The BDI3000 has its own telnet interface and that provides most of the capability you would be seeing through CSAT (except the trace and JTAG boundary scan support).

    There is also a gdb interface provided by BDI3000 which then implements the gdb debugging commands.  So the short answer is CSAT only works with RV-ICE hardware and BDI has its own host independent telnet interface.

    See page 54 of the bdiGDB-ARM11/Cortex User's Guide for information specific to this topic.

     

    Hits : 68
  • KB00153 - Mistral AM/DM37x EVM 14 Pin JTAG Connector wired wrong

    Question:

    I would like to use my BDI probe with a Mistral AM/DM37x EVM (Rev G - OMAP3730).  Your cable # 90050 doesn't seem to match the connector on my board.  Do you offer any other 14 pin cable that is wired for use with this board?

    Answer:

    Yes, If you order Cable # 90053, it is wired per the TI JTAG Spec and can be used as is without any modifications.  Disregard the fact that this is normally for use with boards that use Adaptive Clocking.  This is not revelant in this case.

    Hits : 45
  • KB00149 - i.MX6 Secure JTAG Feature

    Question:

     

    We are currently using the security features of the i.MX6 Processor (HAB) to do secure boot on our product(s).  We are now investigating disabling regular JTAG access in favor of the Secure JTAG feature as outlined in Application Note AN4686.

     

    http://cache.freescale.com/files/32bit/doc/eng_bulletin/AN4686.pdf

     

    We would like to know if Abatron supports this feature on the BDI3000 for the i.MX6.  Or, alternatively, if it is possible for us to implement this with the current firmware.

     

    Answer:

     

    This security feature of the i.MX6 CPU from Freescale is fully supported.  You can use SCANINIT to execute the Challenge/Response sequence to enable JTAG debug. Something like:

     

    SCANINIT  i13=ffff                ;bypass all TAP's
    SCANINIT  i13=0cff                ;Security Output challenge
    SCANINIT  d64=0000000000000000    ;hidden read challenge
    SCANINIT  i13=0dff                ;Security Enter response
    SCANINIT  d64=0123456789abcdef    ;scan in correct response

    To interactively execute this sequence use the JTAG low level commands. This way you can read out the current challenge value.

     

    *********************************************************************************************
    JTAG low level commands:
    ========================

     

    IMX6#0>jtag
    JTAG>help
    TRST  {0|1}                  assert (1) or release (0) TRST
    RST   {0|1}                  assert (1) or release (0) RST
    CLK             clock TAP with requested TMS value
    RIR                     read  IR, zero is scanned in
    RDR                     read  DR, zero is scanned in
    WIR   <...b2b1b0>      write IR, b0 is first scanned
    WDR   <...b2b1b0>      write DR, b0 is first scanned
    XIR   <...b2b1b0>      xchg  IR, b0 is first scanned
    XDR   <...b2b1b0>      xchg  DR, b0 is first scanned
                                 len : the number of bits 1..256
                                 bx  : a data byte, two hex digits
    DELAY <10...50000>           delay for n microseconds
    HELP                         display JTAG command list
    EXIT                         terminate JTAG mode

     

    Hits : 180

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